1. Field of the Invention
This invention relates generally to an apparatus and method for improving image quality and in particular to an apparatus and method for converting binary images to grey-scale or coler images and for converting a series of red, green, and blue analog images to coler, images, and then either displaying those images or driving a spatial light modulator.
More specifically, this invention relates to binary and analog frame buffer pixel devices and to frame buffer type devices and methods for implementing improved methods of displaying images or of driving spatial light modulators.
2. Background of the Related Art
It has been known that when a person views a rapidly cycled through sequence of binary images, the person may, if the rate and duration of images is proper, temporally integrate such that that sequence of binary images and the sequence in turn appears to be grey-scale images. This integration phenomenon is of particular interest with the arrival of high speed binary displays. Such devices are used, for example, in projection display systems, head-up displays and head mounted displays. There exist small fast high resolution displays which are essentially binary in nature such as the Digital Mirror Device (DMD), made by Texas Instruments, active matrix electro-luminescence (AMEL) field emission display (FED) as well as actively addressed ferro-electric liquid crystal devices. These technologies are capable of producing many thousands of binary images per second, depending on the number of pixels per frame, etc. . . .
FIG. 1A shows a series of binary images 105 which could be viewed by a person in the manner described above. Each frame F1-Fm will be comprised of a series of bits that are either 1 (ON) or 0 (OFF). That is, the series F1-Fm of frames as well as each individual frame is actually a series of bits which must eventually be displayed in order to make it possible for the person viewing the binary images to perform the integration discussed above. FIG. 1A further shows pixels Pj in general, and P1-P4, in particular, as representative pixels. As each frame F1-Fm is displayed for a time t, some of the pixels Pj will be a logical 1 and some will be a logical 0. In order for a person to view images produced by frames F1-Fm, a display device is required.
A problem with the above approach is that a display device which displays the group of binary images 105 must be capable of responding in the time t (which relates to the frame rate 1/t). This places a limitation on which displays can be used. Namely, only those display devices can be used which have response rates at least as great as 1/t Hz or frames per second. However, the integration process requires that t be small, otherwise the display would appear to flicker and not appear to provide a grey-scale.
Currently, there are a variety of display devices which might be used to output the above discussed subframes. Liquid crystal on silicon (LCOS) devices which have been designed as displays (or spatial light modulators) have used pixel designs which can be categorized as being either "dynamic" or "static". A static pixel design has a memory element at each pixel, which can store the pixel data indefinitely without the need for periodic refresh cycles. This is analogous to SRAM (static random access memory) in computer memory. A dynamic pixel stores data capacitively and requires a periodic refresh to compensate for leakage of the stored charge, analogous to DRAM (dynamic random access memory).
Both of these types of displays share the property that as the array of pixels is addressed in sequence, row-at-a-time, the liquid crystal begins to update to the new data immediately once the row is addresses. It happens that a reasonably high resolution displays, such as 1024 pixels, the electronic refresh time is comparable or longer than the liquid crystal switching time. For example, if data is supplied to the display through 32 data wires running at 50 M bits/sec, such an array of pixels takes approximately 690 microseconds to update. The liquid crystal switches in approximately 100 microseconds. It is valid, therefore, to view the display as being updated in a sweeping motion across its area.
In some applications, it would be advantageous to have the data on all of the display be simultaneously valid before it can be usefully viewed. Examples of such applications include most coherent applications such as optical correlators, optical precise steerers etc. . . , and display applications where precise synchronization with other parts of the system, such as an illuminated source, is required.
Current pixel designs using liquid crystal displays or microdisplays fall into two major categories, namely, single transistor pixel systems and static pixel systems. There are a number of variations to these types of designs, but all relate generally to one of these two approaches.
FIG. 1B shows a schematic of a single transistor pixel circuit 701 which is part of conventional single transistor pixel array system. Such systems are used in the so-called active matrix type computer screens as well as in some silicon, backplane microdisplays which use liquid crystal displays. The entire array of pixels is formed such that all of the pixels circuits 701 in a row of the display share a gate wire 705 and all of the pixel circuits in a column share a data wire 710 (or vice versa). Each pixel circuit 701 includes a transistor 714 and a pixel mirror or window electrode 718.
Displays using circuit 701 are updated a row-at-a-time. In particular, gate wire 705 is activated, thereby activating all transistors 714 on a single row of pixels on the display. Upon activation of gate wire 705, charge flows through transistor 714, thereby bringing the pixel mirror 718 to the same voltage as data wire 710. Device 718 can be a pixel mirror, electrode window, or pixel electrode and hence these will be used interchangeably throughout this specification. Gate wire 705 is then de-activated, thereby trapping the charge and hence the voltage on pixel mirror 718. The voltage on pixel mirror 718 then switches the liquid crystal (not shown). There is a capacitance associated with pixel mirror 718 and the details of the design of such a pixel often deal with maximizing this capacitance to improve charge storage.
Pixel circuit 701 can be used either as an analog pixel, when the voltages on data wires 710 are driven to intermediate values, or as a binary pixel when these wires are driven to only two values--typically 0 V and 5 V. It must be noted, however, that this pixel display approach is not a frame-buffer pixel as called for in the parent application to this application. That is, the pixel mirrors 718 are updated a row-at-a-time.
The other type of pixel design that has been used is the so-called static pixel displays. Static pixel displays use pixels which contain a data-latch and possibly other circuitry. This approach has been used, for example, by a research group at the University of Edinburgh in Scotland. FIG. 1C shows a schematic of a static pixel circuit 721 referred to as a SRAM pixel. Pixel circuit 721 includes a data latch 732 connected to array gate wire 705 and data wire 710. Pixel circuit 721 also has a pixel mirror or electrode window 718. (Note that gate wire 705 and data wire 710 are given the same reference numbers in FIG. 1C as they had in FIG. 1B.) Here, however, data latch 732 reads the logic level on data wire 710 under the control of gate wire 705. A data bit is stored in data latch 732 in the conventional manner that static latches store data and hence, the data is stored indefinitely without refresh. Output 740 of data latch 732 can be directly connected to pixel mirror 718 or connected to an exclusive-or (X-OR) 750 (as shown) or an exclusive-nor (X-NOR) gate (not shown). Exclusive-or 750 (or the X-NOR) drive a pixel clock (not shown) either in-phase or out-of-phase with a global clock line 755 from a global clock (not shown.
X-OR 750 functions in accordance with the signal 740 output from data latch 732, and consequently functions in accordance with the data bit stored in latch 732. For example, all pixels in the static display device that have a "1" stored in latch 732 take the opposite logic value of global clock signal 755, whereas all pixels in the static display device that have a "0" stored in latch 732 take the same logic value as the global clock signal 755. This was originally done to facilitate d.c. balancing of nematic liquid crystals used in earlier liquid crystal on silicon devices. It has been retained by the Edinburgh group in some of their fast ferroelectric devices to assist with frame-inversion, which is another form of d.c. balancing used with FLC based devices. Hence, once these displays load a frame of data, they have the inverse of that frame available at the pixel mirrors simply by switching the global clock.
This pixel display approach is also not a frame-buffer pixel as called for in the parent application to this application. That is, although the image data are stored on the pixel array, the pixel latches 73 (and hence the pixel mirrors 718) are updated a row-at-a-time, just as in the single transistor case discussed above. Note that this pixel display approach is binary since latch 732 uses restoring logic to pull all nodes in the circuit to either a logic "1" or a logic "0" as does X-OR gate 750.